This invention relates to liquid crystal cells in general, and more particularly to scanning liquid crystal display cells.
There are already known cells of the above type which include picture elements (pels) that are arranged in a matrix array, and in which the liquid crystal layer is sandwiched between an electroded transparent front sheet and a rear sheet formed by or carrying a semiconductive layer provided with access circuitry by which the display is addressed on a line-by-line basis via a matrix array of semiconductor gates directly or indirectly connected with an overlying matrix array of liquid crystal cell electrode pads.
One addressing scheme for driving this type of display cell is described in the specification of British Patent Application Ser. No. 2078422A, to which attention is directed. In that scheme a voltage square wave is applied to the front electrodes in order to increase the available drive voltage across the liquid crystal layer for a given drive voltage within the semiconductive layer; and a method of blanking is disclosed that involves the turning off of all picture elements between consecutive addressings that occur respectively before and after a voltage change of the front electrode. This blanking minimizes the rms voltage seen by `OFF` elements of the display. The scheme is particularly suitable for binary type displays in which picture elements are either fully `ON` or fully `OFF`, and which have a fast data input that allows the reduction in rms voltage seen by `ON` elements of the display to be minimized by having a rewrite period that is short compared with the cycle time of the voltage square wave applied to the front electrode.
The present invention is concerned with an alternative addressing scheme which does not involve the application of an alternating voltage to the front electrode, and so is better suited for some applications in which there is a fixed format of data input which involves relatively longer rewrite periods, such as that encountered in broadcast television. One of the particular problems associated with displaying broadcast television pictures is that the field repetition rate is fixed at 50 Hz, and so refreshes only occur every 20 ms. Retaining a charge on a picture element electrode pad for this period of time without significant voltage droop implies a substantial time constant. The need to avoid a significant voltage droop arises partly from the need to minimize the residual rms voltage seen by `OFF` elements of the display, and partly from the need to minimize the variations in the rms voltage seen by `ON` elements as a result of differences in time constants.
Voltage droop is caused by the combined effect of liquid crystal resistance and transistor leakage, and also depends upon the capacitance associated with the individual electrode pads. This capacitance depends upon the area of the pad, and hence voltage droop increases as the electrode pad size is reduced. The transistor leakage component is typically somewhat variable over the surface of a conventional silicon wafer, and this can cause different rms voltages to be seen by different picture elements at different points in the display when they are supposed to be identical. As the electrode pad size is reduced beneath about 150 .mu.m.times.150 .mu.m, these differences become visually too obtrusive to be satisfactory for many types of applications involving refreshing at 50 Hz. However, displays with electrode pads smaller than this are commercially attractive because many devices can be fabricated from a single semiconducor wafer.
One way of overcoming this problem is to include a storage capacitor at each electrode pad, but this significantly complicates the manufacture, and thereby aggravates the problem of manufacturing yield.